By Madhavan Swaminathan
3D Integration is being touted because the subsequent semiconductor revolution. This booklet presents a finished assurance at the layout and modeling features of 3D integration, in quite, specialise in its electric habit. taking a look from the point of view the Silicon through (TSV) and Glass through (TGV) know-how, the ebook introduces 3DICs and Interposers as a expertise, and provides its program in numerical modeling, sign integrity, energy integrity and thermal integrity. The authors underscored the possibility of this expertise in layout trade codecs and gear distribution.
Readership: Graduate scholars, lecturers, researchers in electric and electronics engineering, laptop engineering, semiconductors and packaging.
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Additional info for Design and Modeling for 3DICs and Interposers (Wspc Series in Advanced Integration and Packaging)
Previously. In the mid 2000s, an important driver was the need to increase memory density which quickly transitioned towards increasing the communication bandwidth between logic and memory for smart phone applications, leading to reduced power. This is an important factor for consumer applications since a reduction in power consumption increases battery life. 5. Moreover long wirebonds connecting to the dies at the top of the tier limit performance due to increased parasitic resistance and inductance, and hence such stacking was limited to memory applications.
From the business side, the interposer provides an attractive solution for reducing the time to market, since ICs fabricated from different processes and domains can be interconnected and provided as a fully tested module as opposed to a single integrated IC. 13. 13(a) for the wide I/O application from Samsung [Kwon, 2011] where the stacked IC (logic + memory) is assembled directly on the package or PCB. 12. This is the first embodiment of using the interposer. Typical TSV diameters in the IC are around 5µm and hence are much larger than the transistors which have feature sizes of 22nm or less.
However, with a CTE of 3ppm/K, the coefficient of thermal expansion can be matched to silicon and hence provides a significant advantage. 3: Properties of Silicon and Glass Interposer [Courtesy: Bandyopadhyay, 2011]. 0043 67 Dielectric System Integration and Modeling Concepts 27 100Ω-cm thereby lowering coupling, but at increased cost. 3 can be used as the dielectric for lining the TSV walls and for wiring as well. An alternative to using the silicon interposer is the glass interposer with similar via diameter, via pitch and high density wiring.