Latchup in CMOS Technology: The Problem and Its Cure (The by R.R. Troutman

By R.R. Troutman

Why a e-book on Iatchup? Latchup has been, and is still, a almost certainly critical CMOS reliability difficulty. This situation is turning into extra common with the ascendency of CMOS because the dominant VLSI expertise, relatively as parasitic bipolar features proceed to enhance at ever smaller dimensions on silicon wafers with ever decrease illness densities. even though many profitable components were advertised, latchup strategies have frequently been advert hoc. even if latchup avoidance strategies were formerly itemized, there was little quantitative evaluate of previous latchup fixes. what's wanted is a extra common, extra systematic remedy of the latchup challenge. as a result wide selection of CMOS applied sciences and the longer term curiosity in latchup, a few total guiding ideas are wanted. Appreciating the range of attainable triggering mechanisms is vital to a true knowing of latchup. This paintings reports the starting place of every and its impression at the parasitic constitution. each one triggering mechanism is assessed in keeping with a brand new taxonomy.

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Additional info for Latchup in CMOS Technology: The Problem and Its Cure (The Springer International Series in Engineering and Computer Science)

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If the resulting ohmic drop in the substrate is large enough, this can lead to snapback, even in NMOS technologies [Kennedy-731. If the source is turned on hard enough, a sufficient number of injected electrons might be collected by the N-well (some fraction of them are collected at the N-channel FET drain) to turn on the vertical PNP. An avalanching P-channel drain produces an N-well current that tends to forward bias the P+ source. This can also lead to snapback, although the problem for P-channel devices is not as serious as for N-channel, because of an inherently more gradual doping gradient for the P+ diffusions (resulting in a lower peak electric field) and because of a lower ionization rate for holes.

A similar schematic has also been used to model the PNPN structure when the N+ and P+ diffusions in the well are reversed [Fang-84]. In that case the ohmic drop created by current flowing through the well junction to the well contact can be significantly less than the drop created if the same current flowed under the P+ diffusion to a well contact on the other side. RS1 Figure 2-7. Rs2 Lumped element model for distributed N-well collection. This version accounts for distributed collection of lateral base current by the N -well.

This parasitic ┬ĚN-channel FET can be either gated or ungated, with oxide charge causing channel current in the latter case. The effect of a parasitic N-channel device when it turns on is similar to punchthrough, and its effect can be represented by a current source in parallel with lpts in Figure 3-3. Parasitic channel current through the N-well then tends to turn on the vertical PNP. Technically, the lateral NPN is already on if PET current is flowing since the N+ Isubstrate junction is already forward biased at the surface by the gate of the parasitic PET.

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