Download E-books Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs PDF

By Kanupriya Gulati

Single-threaded software program purposes have ceased to determine signi?cant profits in p- formance on a general-purpose CPU, in spite of additional scaling in very huge scale integration (VLSI) know-how. it is a signi?cant challenge for digital layout automation (EDA) functions, because the layout complexity of VLSI built-in circuits (ICs) is regularly becoming. during this study monograph, we assessment customized ICs, ?eld-programmable gate arrays (FPGAs), and portraits processors as structures for accelerating EDA algorithms, rather than the general-purpose sing- threaded CPU. We research purposes that are utilized in key time-consuming steps of the VLSI layout ?ow. extra, those purposes even have diversified levels of inherent parallelism in them. We examine either control-dominated EDA purposes and keep an eye on plus information parallel EDA functions. We speed up those functions on those assorted systems. We additionally current an automatic process for accelerating yes uniprocessor functions on a pix processor. This monograph compares customized ICs, FPGAs, and photos processing devices (GPUs) as power structures to speed up EDA algorithms. It additionally offers info of the programming version used for interfacing with the GPUs.

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6. four. 1 SurveySAT and the GPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. four. 2 MiniSAT improved with Survey Propagation (MESP) . . . 6. five Experimental effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. 6 bankruptcy precis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii eighty three eighty three eighty three eighty five 87 87 ninety three ninety six ninety eight ninety eight half III regulate Plus info Parallel functions 7 Accelerating Statistical Static Timing research utilizing pix Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a hundred and five 7. 1 bankruptcy evaluate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . one hundred and five 7. 2 advent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7. three earlier paintings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7. four Our procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7. four. 1 Static Timing research (STA) at a Gate . . . . . . . . . . . . . . . . 109 7. four. 2 Statistical Static Timing research (SSTA) at a Gate . . . . . . 112 7. five Experimental effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7. 6 bankruptcy precis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 eight Accelerating Fault Simulation utilizing images Processors . . . . . . . . . . 119 eight. 1 bankruptcy review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 eight. 2 advent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 eight. three past paintings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 eight. four Our technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 eight. four. 1 good judgment Simulation at a Gate . . . . . . . . . . . . . . . . . . . . . . . . . . 123 eight. four. 2 Fault Injection at a Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . one hundred twenty five eight. four. three Fault Detection at a Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 eight. four. four Fault Simulation of a Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 127 eight. five Experimental effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 eight. 6 bankruptcy precis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 nine Fault desk new release utilizing pix Processors . . . . . . . . . . . . . . . . . 133 nine. 1 bankruptcy evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 nine. 2 advent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 nine. three earlier paintings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 nine. four Our procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 xviii Contents nine. four. 1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 nine. four. 2 Algorithms: FSIM∗ and GFTABLE . . . . . . . . . . . . . . . . . . . 139 nine. five Experimental effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 nine. 6 bankruptcy precis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a hundred and fifty References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10 Accelerating Circuit Simulation utilizing portraits Processors . . . . . . . . . 153 10. 1 bankruptcy evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 10. 2 creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 10. three past paintings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a hundred and fifty five 10. four Our strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10. four. 1 Parallelizing BSIM3 version Computations on a GPU .

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