By Alexander Supalov, Andrey Semin, Christopher Dahnken, Michael Klemm
Optimizing HPC purposes with Intel® Cluster instruments takes the reader on a travel of the fast-growing region of excessive functionality computing and the optimization of hybrid courses. those courses regularly mix dispensed reminiscence and shared reminiscence programming types and use the Message Passing Interface (MPI) and OpenMP for multi-threading to accomplish the final word objective of excessive functionality at low energy intake on enterprise-class workstations and compute clusters.
The booklet makes a speciality of optimization for clusters inclusive of the Intel® Xeon processor, however the optimization methodologies additionally observe to the Intel® Xeon Phi™ coprocessor and heterogeneous clusters blending either architectures. in addition to the educational and reference content material, the authors handle and refute many myths and misconceptions surrounding the subject. The textual content is augmented and enriched via descriptions of real-life situations.
What you’ll learn
- Practical, hands-on examples convey tips to make clusters and workstations in line with Intel® Xeon processors and Intel® Xeon Phi™ coprocessors "sing" in Linux environments
- How to grasp the synergy of Intel® Parallel Studio XE 2015 Cluster variation, inclusive of Intel® Composer XE, Intel® MPI Library, Intel® hint Analyzer and Collector, Intel® VTune™ Amplifier XE, and plenty of different worthwhile tools
- How to accomplish quick and tangible optimization effects whereas refining your realizing of software program layout principles
Who this ebook is for
software program execs will use this e-book to layout, improve, and optimize their parallel courses on Intel systems. scholars of desktop technological know-how and engineering will worth the booklet as a entire reader, appropriate to many optimization classes provided world wide. The beginner reader will get pleasure from an intensive grounding within the intriguing global of parallel computing.
Table of Contents
Foreword by means of Bronis de Supinski, CTO, Livermore Computing, LLNL
Chapter 1: No Time to learn this Book?
Chapter 2: review of Platform Architectures
Chapter three: Top-Down software program Optimization
Chapter four: Addressing process Bottlenecks
Chapter five: Addressing program Bottlenecks: dispensed Memory
Chapter 6: Addressing software Bottlenecks: Shared Memory
Chapter 7: Addressing program Bottlenecks: Microarchitecture
Chapter eight: software layout Considerations
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Additional resources for Optimizing HPC Applications with Intel Cluster Tools: Hunting Petaflops
Hence, the Haswell microarchitecture that's the foundation for Intel Xeon E3-1200 v3 processors is particularly assorted from the Silvermont microarchitecture used to construct cores for Intel Atom C2000 processors. certain microarchitecture adjustments and particular optimization suggestions are defined within the Intel sixty four and IA-32 Architectures Optimization Reference guide. 12 This 600-page rfile describes a great number of Intel x86 cores and explains how one can optimize software program for IA-32 and Intel sixty four structure processors. The addendum to the aforementioned Intel sixty four and IA-32 Architectures Optimization Reference guide comprises info priceless for quantitative research of the common latencies and throughputs of the person processor directions. the first aim of this knowledge is to assist the programmer with the choice of the guideline sequences (to reduce chain latency) and within the association of the directions (to help in processing). even though, this knowledge additionally presents an knowing of the size of functionality impression from numerous guideline offerings. for example, standard mathematics guide latencies (reported within the variety of clock cycles which are required for the execution middle to accomplish the execution of the guide) are one to 5 cycles (or zero. 4-2 ns while working at 2. five GHz) for easy directions equivalent to addition, multiplication, taking greatest or minimal worth. Latency can achieve as much as forty five cycles (or 18 ns at 2. five GHz) for department of double precision floating element numbers. guideline throughput is mentioned because the variety of clock cycles that have to cross ahead of the problem ports can settle for an analogous guideline back. This is helping to estimate the time it will take, for instance, for a loop new release to accomplish in presence of a cross-loop dependency. for lots of directions, throughput of an guide might be considerably smaller than its latency. occasionally latency is given as only one half the clock cycle. this happens just for the double-speed execution devices present in a few microprocessors. an analogous guide presents estimates for the best-case latencies and throughput of the devoted caches: the 1st (L1) and the second one (L2) point caches, in addition to the interpretation lookaside buffers (TLBs). quite, at the most up-to-date Haswell cores, the burden latency from L1 info cache might differ from 4 to seven cycles (or 1. 6-2. eight ns at 2. five GHz), and the height bandwidth for facts is the same as sixty four (Load) + 32 (Store) bytes consistent with cycle, or as much as 240 GB/s combination bandwidth (160 GB/s to load info and eighty GB/s to shop the data). The structure of contemporary Intel processors helps versatile integration of a number of processor cores with a shared uncore subsystem. Uncores often include built-in DRAM (Dynamic Random entry reminiscence) controllers, PCI show I/O, quickly direction Interconnect (QPI) hyperlinks, and the built-in photos processing devices (GPUs) in a few types, in addition to a shared cache (L2 or L3, reckoning on the processor, that is known as the final point Cache, or LLC).